1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to a technique for debugging an integrated circuit having a parallel scan-chain architecture.
2. Related Art
Scan-based design techniques are often used so that integrated circuit devices can be tested. An integrated circuit device designed using scan-based design techniques operates in two modes: normal mode and testing mode. When operating in normal mode, the integrated device performs the functions that it was designed to perform. When operating in testing mode, the integrated circuit device can be tested. Testing mode typically includes the following sub-modes: scan mode and capture mode. When operating in scan mode, the storage elements (e.g., flip-flops) within the integrated circuit device are connected to one another to form one or more scan-chains. When operating in capture mode, the storage elements are connected to one another and/or to combinational logic in the same fashion that they would be if operating in normal mode.
There are two common scan-chain architectures: serial and parallel. FIG. 1 shows an integrated circuit device 100 having a serial scan-chain architecture. Integrated circuit device 100 can be tested as follows. First, integrated circuit device 100 is placed in scan mode. This causes a single scan-chain to be formed using some or all of the storage elements 120 within integrated circuit device 100. Second, test data bits are scanned into the storage elements 120 via scan input signal line SI. Third, integrated circuit device 100 is placed in capture mode. Fourth, integrated circuit device 100 is allowed operate for one or more clock cycles in capture mode. This allows the functionality of the storage elements 120 and any combinational logic connected to storage elements 120 to be tested. Fifth, integrated circuit device 100 is placed in scan mode. Sixth, the data bits that reside in storage elements 120 (i.e., the resulting data bits) are scanned out of integrated circuit device 100 via scan output signal line SO. Seventh, the resulting data bits are compared to expected data bits to determine whether there are any faults, i.e., whether any of storage elements 120 or any combinational logic (not shown) connected to storage elements 120 is not operating properly.
A problem with the serial scan-chain architecture of integrated circuit device 100 is that it requires a very large number of test data bits to be generated to test integrated circuit device 100. Another problem with the serial scan-chain architecture of integrated circuit device 100 is that it requires a very large amount of time to test integrated circuit device 100. To address these problems, parallel scan-chain architectures have been developed.
FIG. 2 shows an integrated circuit device 200 having a parallel scan-chain architecture. Integrated circuit device 200 includes multiple scan-chain branches 210 (separately labeled 210-1, 210-2, . . . , 210-N). Each scan-chain branch 210 includes some of the storage elements 220 on integrated circuit device 210. Integrated circuit device 200 can be tested as follows. First, integrated circuit device 200 is placed in scan mode. Second, test data bits are scanned into storage elements 220 of each scan-chain branch 210 via scan input signal line SI. As a result, identical test data bits are stored in storage elements 220 of each scan-chain branch 210. Third, integrated circuit device 200 is placed in capture mode. Fourth, integrated circuit device 200 is allowed operate for one or more clock cycles in capture mode. This allows the functionality of the storage elements 220 and any combinational logic connected to storage elements 220 to be tested. Fifth, integrated circuit device 200 is placed in scan mode. Sixth, the data bits that are stored in storage elements 220 of each scan-chain branch 210 (i.e., the resulting data bit streams) are scanned out of each scan-chain branch 210, combined using combiner 230 (e.g., an XOR gate), and output via signal line SO. Note that combiner 230 combines the resulting data bit streams output by each scan-chain branch 210 and generates a single common resulting data bit stream that is output via signal line SO. Seventh, the common resulting bit stream is compared to an expected data bit stream to determine whether there are any faults, i.e., whether any of storage elements 220 or any combinational logic (not shown) between storage elements 220 is not operating properly.
A problem with the parallel scan-chain architecture of integrated circuit device 200 is that if there is a fault either in scan mode or capture mode, it is difficult to determine which scan-chain branch or branches 210 is/are not operating properly. This is because the resulting data bit streams output by each scan-chain branch 210 are combined into a single common resulting data bit stream. As a result, if a fault occurs in one of the scan-chain branches 210, it is difficult to identify the scan-chain branch or branches 210 that have the fault and thus it is difficult to pinpoint the location of the fault(s) within integrated circuit device 200.
Accordingly, what is needed is a technique for debugging an integrated circuit device having a parallel scan-chain architecture.